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HN28F101 Series
131072-word x 8-bit CMOS Flash Memory
ADE-203-122J (Z) Rev. 10.0 Nov. 15, 1996 Description
The Hitachi HN28F101 is a 131072-word x 8-bit CMOS flash Memory, realizing on-board programming. It programs or erases data with only on-board power supply (12 V V PP supply/5 V VCC supply). It programs data with fast programming algorithm by command inputs. It has two types of erase algorithm : automatic erase and fast erase by command inputs. Automatic erase function can erase data automatically without external control only by inputting trigger pulse and inform erase completion to CPU by status polling. The HN28F101 can control programming erase algorithm externally.
Features
* On-board power supply (VCC/VPP ) VCC = 5 V 10% VPP = VSS to VCC (Read) VPP = 12.0 V 0.6 V (Erase/Program) * Fast access time 120 ns/150 ns/200 ns (max) * Programming function Byte programming Programming time: 25 s typ/byte Address, data, control latch function * On-board automatic erase function Chip erase Erase time: 1 s typ Address, data, control latch function Status polling function * Low power dissipation ICC = 10 mA typ (Read) ICC = 20 A max (Standby) IPP = 30 mA typ (Auto erase/Program) IPP = 20 A max (Read/Standby)
HN28F101 Series
* Erasing endurance: 10,000 times * Pin arrangement: 32-pin JEDEC standard * Package 32-pin SOP 32-pin TSOP
Ordering Information
Type No. HN28F101FP-12 HN28F101FP-15 HN28F101FP-20 HN28F101T-12 HN28F101T-15 HN28F101T-20 HN28F101R-12 HN28F101R-15 HN28F101R-20 Access Time 120 ns 150 ns 200 ns 120 ns 150 ns 200 ns 120 ns 150 ns 200 ns Package 32-pin plastic SOP (FP-32D)
32-pin plastic TSOP (TFP-32DA)
32-pin plastic TSOP (TFP-32DAR)
Pin Arrangement
HN28F101FP Series VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
2
HN28F101 Series
Pin Arrangement (cont)
HN28F101T Series
A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
(Top view) HN28F101R Series
OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 A14 NC WE VCC VPP A16 A15 A12 A7 A6 A5 A4
(Top view)
Pin Description
Pin Name A0-A16 I/O0-I/O7 CE OE WE VCC VPP VSS Function Address Input/output Chip enable Output enable Write enable Power supply Programming power supply Ground
3
HN28F101 Series
Block Diagram
A5 A9 A12 A16 Address Latch X- Decoder 1024 X 1024 Memory Matrix
I/O0 I/O7
Data Latch
Input Data Control
Y - Gating Y - Decoder
Address Latch
CE OE WE V V V
CC
R/W/E Control A0 - A4, A10, A11
H
PP SS
: High Threshold Inverter
H
Latch
4
HN28F101 Series
Mode Selection
Pin VPP Mode Read SOP, TSOP Read Output disable Standby Identifier* Command program Read* *
3, 5 1
CE (22) (30) VIL VIL VIH VIL VIL VIL VIH VIL
OE (24) (32) VIL VIH X VIL VIL VIH X VIH
WE (31) (7) VIH VIH X VIH VIH VIH X VIL
A9 (26) (2) A9 X X VH * A9 X X A9
2
I/O0 - I/O7 (13 - 15, 17 - 21) (21 - 23, 25 - 29) Dout High-Z High-Z ID Dout High-Z High-Z Din
(1) (9) VCC* 6 VCC VCC VCC VPP VPP VPP VPP
Output disable Standby Write*
4
Notes: 1. Device identifier code can be output in command programming mode. Refer to the table of command address and data input. 2. VH : 11.5 V H 12.5V. 3. Data can be read when 12 V is applied to VPP. Device identifier code can be output by command inputs. 4. Refer to the table of command address and data input. Data is programmed, erased, or verified after mode setting by command inputs. 5. Status of automatic erase can be verified in this mode. Status outputs on I/O7. I/O0 to I/O6 are in high impedance state. 6. X : V IH or VIL. V PP = 0 V to VCC
5
HN28F101 Series
Command Address and Data Input
First cycle Command Read (memory)*4 The number of cycle 1 Operation mode*1 Write Write Write Write Write Write Write Write Address* 2 x x x EA x x x x Data*3 00H 90H 20H A0H 30H 40H C0H FFH Second cycle Operation mode*1 Read Read Write Read Write Write Read Write Address* 2 Data*3 RA IA x x x PA x x Dout ID 20H EVD 30H PD PVD FFH
Read identified codes 2 Setup erase/erase* Erase verify*
5 5
2 2 2 2 2 2
Setup auto erase/ auto erase*6 Setup program/ program*7 Program verify*7 Reset
Notes: 1. Refer to command program mode in mode selection about operation mode. 2. Refer to device identifier mode. IA = Identifier address, PA = Programming address, EA = Erase verify address, RA = Read address 3. Refer to device identifier mode. PA are latched by programming command. ID = Identifier output code, PD = Programming data, PVD = Programming verify output data, EVD = Erase verify output data 4. Command latch default value when applying 12 V to VPP is "00H". Device is in read mode after VPP is set 12 V (before other command is input). 5. All data in chip are erased. Erase data according to fast high-reliability erase flowchart. 6. All data in chip are erased. Data are erased automatically by internal logic circuit. External erase verify is not required. Erasure completion must be verified by status polling after automatic erase starts. 7. Program data according to fast high-reliability programming flowchart.
Absolute Maximum Ratings
Parameter All input and output voltage* VPP voltage*
1 1 1
Symbol Vin, Vout VPP VCC Topr Tstg Tbias
3
Value -0.6* to +7.0 -0.6 to +14.0 -0.6 to +7.0 0 to +70 -55 to +125 -10 to +80
2
Unit V V V C C C
VCC voltage*
Operating temperature range Storage temperature range*
Storage temperature under bias
Notes: 1. Relative to VSS . 2. Vin, Vout, V ID min = -2.0 V for pulse width 20 ns. 3. Device storage temperature range before programming.
6
HN28F101 Series
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol Cin Cout Min -- -- Typ -- -- Max 6 12 Unit pF pF Test conditions Vin = 0 V Vout = 0 V
Read Operation
DC Characteristics (VCC = 5 V 10%, VPP = VCC~VSS, Ta = 0 to +70C)
Parameter Input leakage current Output leakage current VPP current Standby V CC current Symbol Min I LI I LO I PP1 I SB1 I SB2 Operating VCC current
3
Typ -- -- -- -- -- 6 10
1
Max 2 2 20 1 20 15 30 0.8 VCC + 0.3* 0.45 --
2
Unit A A A mA A mA mA V V V V
Test conditions Vin = 0 to VCC Vout = 0 to VCC VPP = 5.5 V CE = VIH CE = VCC Iout = 0 mA, f = 1 MHz Iout = 0 mA, f = 8 MHz
-- -- -- -- -- -- -- -0.3* 2.2 -- 2.4
I CC1 I CC2
Input voltage*
VIL VIH
-- -- -- --
Output voltage
VOL VOH
I OL = 2.1 mA I OH = -400 A
Notes: 1. VIL min = -2.0 V for pulse width 20 ns. 2. VIH max = VCC + 1.5 V for pulse width 20 ns. If V IH is over the specified maximum value, read operation cannot be guaranteed. 3. Only defined for DC and long cycle function test. VIL max = 0.45 V, VIH min = 2.4 V for AC function test.
7
HN28F101 Series
AC Characteristics (VCC = 5 V 10%, VPP = VSS to VCC, Ta = 0 to +70C)
Test Conditions * * * * Input pulse levels: 0.45 V/2.4 V Input rise and fall time: 10 ns Output load: 1TTL Gate + 100 pF (Including scope and jig.) Reference levels for measuring timing: 0.8 V, 2.0 V
HN28F101-12 HN28F101-15 HN28F101-20 Parameter Address to output delay CE to output delay OE to output delay OE high to output float* Address to output hold Note:
1
Symbol Min t ACC t CE t OE t DF t OH -- -- -- 0 5
Max 120 120 60 40 --
Min -- -- -- 0 5
Max 150 150 70 50 --
Min -- -- -- 0 5
Max 200 200 80 60 --
Unit Test conditions ns ns ns ns ns CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = OE = VIL
1. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
Read Timing Waveform
Address CE Standby Mode t CE OE High WE t ACC Data Out t OE t DF t OH Data Out Valid Active Mode Standby Mode
8
HN28F101 Series
Command Programming/Data Programming/Erase Operation
DC Characteristics (VCC = 5 V 10%, VPP = 12.0 V 0.6 V, Ta = 0 to +70C)
Parameter Input leakage current Output leakage current Standby V CC current Symbol I LI I LO I SB1 I SB2 Operating VCC current Read I CC1 I CC2 Program Erase I CC3 I CC4 I CC5 VPP current Read Program Erase I PP1 I PP2 I PP3 I PP4 Input voltage VIL VIH Output voltage VOL VOH Min -- -- -- -- -- -- -- -- -- -- -- -- -- - 0.3* 2.2 -- 2.4
4
Typ -- -- -- -- 6 10 2 10 5 -- 5 35 10 -- -- -- --
Max 2 2 1 200 15 30 10 40 15 1 30 80 30 0.8
5
Unit A A mA A mA mA mA mA mA mA mA mA mA V
Test conditions Vin = 0 V to VCC Vout = 0 V to VCC CE = VIH CE = VCC Iout = 0 mA, f = 1 MHz Iout = 0 mA, f = 8 MHz
In automatic erase In high-reliability erase VPP = 12.6 V In programming In automatic erase In high-reliability erase
VCC + 0. 3* V 0.45 -- V V I OL = 2.1 mA I OH = -400 A
9
HN28F101 Series
Notes: 1. VCC/V PP power on/off timing VCC must be applied before or simultaneously VPP , and removed after or simultaneously VPP . This V CC/V PP power on/off timing must be satisfied at VCC/VPP on/off caused by power failure.
5V VCC 0V 0s min 12V 0s min
VPP
5V
0V 2. VPP must not exceed 14 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12 V. 4. VIL min = -1.0 V for pulse width 20 ns. 5. If V IH is over the specified maximum value, programming operation cannot be guaranteed.
10
HN28F101 Series
AC Characteristics (VCC = 5 V 10%, VPP = 12.0 V 0.6 V, Ta = 0 to +70C)
Test Conditions * * * * Input pulse levels: 0.45 V/2.4 V Input rise and fall time: 10 ns Output load: 1TTL Gate + 100 pF (Including scope and jig.) Reference levels for measuring timing: 0.8 V, 2.0 V
HN28F101-12 HN28F101-15 HN28F101-20 Parameter Command programming cycle time Address setup time Address hold time Data setup time Data hold time CE setup time CE hold time VPP setup time VPP hold time Symbol Min t CWC t AS t AH t DS t DH t CES t CEH t VPS t VPH 120 0 60 50 10 0 50 100 100 70 40 0 6 -- -- 120 -- 25 9 0 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 120 300 -- 120 -- 11 40 30 Min 150 0 60 50 10 0 50 100 100 70 40 0 6 -- -- 120 -- 25 9 0 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 150 300 -- 150 -- 11 50 30 Min 200 0 60 50 10 0 50 100 100 80 40 0 6 -- -- 120 -- 25 9 0 -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- 200 300 -- 200 -- 11 60 30 Unit Test conditions ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns s ms ns s
WE programming pulse width t WEP WE programming pulse high t WEH time OE setup time before command programming OE setup time before verify Verify access time Verify access time in erase OE setup time before status polling Status polling access time Standby time before programming Standby time in erase Output disable time*
3
t OEWS t OERS t VA t VAE t OEPS t SPA t PPW t ET t DF
Total erase time in automatic t AET erase*3
11
HN28F101 Series
Notes: 1. CE, OE, and WE must be fixed high during VPP transition from 5 V to 12 V or from 12 V to 5 V. 2. Refer to read operation when VPP = VCC about read operation while VPP = 12 V. 3. t DF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 4. Address are taken into on the falling edge of write-enable pulse and addresses are latched on the rising edge of write-enabke pulse during chip-enable is low. Data is latched on the rising edge of write-enable pulse during chip-enable is low.
Erase and Program Time
Erase and program mode Chip (128 kB) erase time Auto erase mode Fast high-reliability erase mode* Chip (128 kB) program time Notes: 1. 2. 3. 4. 5.
2, 3 3
Min -- -- --
Typ*4 1 0.6 5
Max 30 30 81*
5
Unit second second second
Fast high-reliability program mode*
Each values are same for all read access version. Excludes pre-write process before erasure and verify process (6 s x 128 kB). Excludes system overhead. Ta = 25C, V PP = 12 V, VCC = 5 V Theoretical value calculated from fast high-reliability programming flowchart. (25 s program + 6 s verify) x 20 times x 128 kB = 81 second.
12
HN28F101 Series
Automatic Erase Timing Waveform
Setup auto erase VCC VPP 12 V 5.0 V 5.0 V t VPS t VPH Auto erase & status polling
Address CE t CEH OE
t OEWS
t CES t OEPS
t CES t WEP
t CWC
t CES t CEH
t WEP
t AET t DF
WE t DS I/O7 t DH
Command in
t WEH t DS t DH
Command in
t SPA
Status polling I/O0 - I/O6
Command in Command in
Status Polling Status polling allows the status of the flash memory to be determined. If the flash memory is set to the status polling mode during erase cycle, I/O7 pin is lowered to VOL level to indicate that the flash memory is performing erase operation. I/O7 pin is set to the VOH level when erase operation has finished. Notes: In automatic erase mode, the device automatically processes to pre-write all "0" before erasing. Therefore, it is not required to pre-write by fast high-reliability programming.
13
HN28F101 Series
Fast High-Reliability Programming
This device can be applied the fast high-reliability programming algorithm shown in following flowchart. This algorithm allows to obtain fasterprogramming time without any voltage stress to the device nor deterioration in reliability of programmed data.
START Apply VPP= 12.0 0.6 V Address = 0
n=0
n + 1 n Write setup program command
Write program address and data Wait 25 s
Write program verify command Address + 1 Address
Wait 6 s
Verify GO NO LAST Address ? YES Apply VPP = VCC
NOGO
n = 20 YES
NO
END
FAIL
Fast High-Reliability Programming Flowchart
14
HN28F101 Series
Notes: In case of two or more devices are programmed simultaneously, following steps should be applied to avoid over programming for the verified device. (1) Write set up program command to FFH, (2) Write program command to FFH, (3) Write program verify command to 00H and program verify address to read address.
Fast High-Reliability Programming Timing Waveform
Setup program VCC VPP 5.0 V 12 V 5.0 V t VPS tVPH Address valid tAH
Program
Program verify
Address t AS CE
t CEH OE t OEWS WE tDS I/O7
Command in
t CES
tCWC t PPW tCES t WEP
t CES t WEP
tWEP t CEH
t CEH t OERS t DF Data out valid
t WEH tDH tDS
Data in
tDH tDS
tDH
Command in
t VA
I/O0 to I/O6
Command in
Data in
Command in
Data out valid
Notes: The data output level during program verification may result in an intermediate level between V0H and VOL due to an insufficiently programmed.
15
HN28F101 Series
Fast High-Reliability Erase
This device can be applied the fast high-reliability erase algorithm showm in following flowchart. This algorithm allows to obtain faster erase time without any voltage any voltage stress to the device nor deterioration in reliability of data.
START YES
All bits DATA = 00H? NO All bits program 00H *1 Set address n=0 n+1 n
Write setup erase / erase command
Wait 10 ms
Write erase verify command Address + 1 Address Wait 6 s
Verify YES
NO
NO NO LAST Address ? YES END FAIL n = 3000 YES
*1. Program data to all bits according to fast high-reliability erasing flowchart.
Fast High-Reliability Erasing Flowchart
16
HN28F101 Series
Notes: In case of two or more devices are erased simultaneously, following steps should be applied to avoid over erase for verified device. (1) Write set up erase command to A0H and set erase verify address to verify address. (2) Write erase command to A0H. (3) Write erase verify command to A0H.
Erase Timing Waveforms
Setup erase VCC VPP 5.0 V Address 5.0 V 12 V t VPS Address valid t AS tAH t VPH Erase Erase verify
CE
OE
tOEWS t WEP t CES
t CWC t CES tCEH
t CEH t WEP
t CES t ET t WEP
t CEH t OERS t VAE
WE t DS t DH I/O0 to I/O7 Command in Command in Command in t WEH t DS t DH t DS t DH Data out valid t DF
Notes: The data output level during erasure verification may result in an intermediate level between VOH and VOL due to an insufficiently erased.
17
HN28F101 Series
Mode Description
Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of flash memory. By this mode, the device will be automatically matched its own corresponding erase and programming algorithm, using programming equipment. HN28F101 Series Identifier Code
Pins SOP, TSOP A0 (12) (20) VIL VIH I/O7 (21) (29) 0 0 I/O6 (20) (28) 0 0 I/O5 (19) (27) 0 0 I/O4 (18) (26) 0 1 I/O3 (17) (25) 0 1 I/O2 (15) (23) 1 0 I/O1 (14) (22) 1 0 I/O0 (13) (21) 1 1
Identifier
Hex Data 07 19
Manufacturer code Device code
Notes: 1. Device identifier code can be read out by applying 12.0 V 0.5 V to A9 when VPP = VCC, or inputting command while VPP is 12 V. 2. A1 to A8, A10 to A16, and CE = OE = VIL, WE = VIH 3. VCC = VPP = 5 V 10%
18
HN28F101 Series
Package Dimensions
HN28F101FP Series (FP-32D)
20.45 20.95 Max 32 17 Unit: mm
1 1.00 Max
16 3.00 Max
+ 0.13 - 0.07
11.30
14.14 0.30 1.42
0.22
1.27
0.10 0.40 + 0.05 -
0.10 0.15 M
+ 0.12 - 0.10
0-8 0.80 0.20
0.15
19
HN28F101 Series
HN28F101T Series (TFP-32DA)
8.00 8.20 Max 32 17 Unit: mm
1 0.20 0.10
16 0.50 0.08 M 14.00 0.20 0.80 0-5 0.50 0.10
0.45 Max 0.17 0.05 1.20 Max
12.40
0.10
HN28F101R Series (TFP-32DAR)
8.00 8.20 Max 17 32
0.13 0.05
Unit: mm
16 0.20 0.10
1 0.50 0.08 M 14.00 0.20 0.80 0-5 0.50 0.10
0.45 Max 0.17 0.05 1.20 Max
12.40
0.10
20
0.13 0.05
HN28F101 Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
21
HN28F101 Series
Revision Record
Rev. 1.0 2.0 Date Sep. 20, 1990 Dec. 24, 1990 Contents of Modification Initial issue Drawn by Approved by K. Furusawa T. Wada
K. Furusawa T. Wada P1 Erasing endurance: 10000 times P3, 4, 17 Addition of 32-pin PLCC package (CP-32) P9 t OERS min: 5/5/5 s to 6/6/6 s t PPW min: 15/15/15 s to 25/25/25 s max: 25/25/25 s to not specified P11 Change of fast high reliability programming flowchat P13 Change of fast high reliability erase flowchart P1, 8, 9, 11 VPP : 12V 0.4 V to 12 V 0.6 V P6 VPP : -0.6 to 13 V to -0.6 to 14 V P10, 12, 14 Change of timing waveforms Addition of t WEH Change of type no. HN29C1001B to HN28F101 Change of fast high reliability programing timing waveform Change of Low power dissipation I CC typ (Read): 30 mA to 10 mA P8, 10 DC Characteristics Change of I CC2 typ: 25 mA to 10 mA I CC2 max: 50 mA to 30 mA VIH max: VCC + 1 V to VCC + 0.3 V AC Characteristics t WEH min: 20 ns to 40 ns t OEPS min: 20 ns to 120 ns K. Furusawa T. Wada
3.0
Feb. 19, 1991
4.0
Jun. 20, 1991
K. Furusawa T. Wada
5.0
Oct. 20, 1991
K. Furusawa T. Wada
6.0 7.0
Nov. 25, 1991 Nov. 11, 1992
P1,3,19 Addition of 32-pin plastic TSOP (TFP-32D) K. Furusawa T. Wada P1,3,19 Addition of 32-pin plastic TSOP (TFP-32DR) Deletion of 32-pin plastic TSOP (TFP-32D) Deletion of 32-pin plastic TSOP (TFP-32DR) Mode selection Addition of pin number (DIP, SOP, PLCC) Addition of pin number (TSOP) Change of notes 5 DC Characteristics Change of I SB , I CC3, I PP1 Change of automatic erase timing waveform Addition of notes from P12, P16 AC Characteristics Change of t CEH Change of fast high reliability programming timing waveform Change of fast high reliability programming flowchat Change of erase timing waveform K. Furusawa T. Wada
22
HN28F101 Series
Revision Record (cont.)
Rev. 7.0 Date Nov. 11, 1992 Contents of Modification Mode Description Addition of pin number (DIP, SOP, PLCC) Addition of pin number (TSOP) Change of notes 1 Addition of HN28F101TD Series (TFP-32D) Addition of HN28F101RD Series (TFP-32DR) Change of Read Timing Waveform Deletion of old type name (HN29c101B) DC Characteristics I CC3 typ: 9 mA to 2 mA Change of note1 AC Characteristics Addiditon of t VAE max: 300/300/300 ns t AET min: 0.5/0.5/0.5 s to --/--/-- s Addition of Erase and program Time Change of Timing Waveform Change of format Deletion of HN28F101P/CP/TD/DR Series Drawn by Approved by K. Furusawa T. Wada
8.0
Aug. 20, 1993
K. Izawa
O. Sakai
9.0
Apr. 20, 1994
Y. Mori
K. Furusawa
10.0
Nov. 15, 1996
23

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